If you’re selecting a PCB Fabrication Service, understanding how vias formed in PCBs is one of the fastest ways to assess manufacturing capability and long-term reliability. Vias don’t simply “appear” by referring Gerber files—they are created through a controlled PCB manufacturing process that includes drilling, chemical preparation, copper deposition, and inspection. This guide is going to narrate process-first (not marketing-first) and explains how via formation actually works, where failures come from, and what designers should do to avoid them.
1. Introduction: Why Via Formation Matters More Than Via Types
Most articles start by listing via types—through, blind, buried, microvia—and stop there. But in real production, the type matters less than how it’s formed. A via is not “just a hole.” A via is a plated electrical interconnect that must survive assembly heat, thermal cycling, vibration, and the electrical stress of fast signals and high current.
Via formation directly affects:
● Electrical reliability: a via barrel must be continuous, thick enough, and well-adhered to survive fatigue.
● Signal integrity: via geometry and plating uniformity influence impedance, reflections, and EMI.
● Thermal performance: copper thickness and via filling determine how effectively heat moves through the board.
● Assembly yield: poorly formed vias can cause solder wicking, voiding, or pad separation during reflow.
A large share of “mystery failures” in PCBs can be traced back to via formation defects—voids, thin copper, cracks, contamination, or misregistration. This guide covers the full formation workflow so you can connect design decisions to manufacturing outcomes.
2. What Does “Via Formation” Mean in PCB Manufacturing?
Via formation is the manufacturing process that turns a planned via location (in your design files) into a functional, plated interconnect inside a physical PCB.
It’s different from via design:
● Via design defines size, location, and type in CAD.
● Via formation is how the factory produces the actual conductive structure.
A simple but important distinction:
● Mechanical hole: a drilled opening in resin/glass (not conductive).
● Electrically plated interconnect: the same hole after it has a copper “barrel” connected to inner layers.
Via formation is tightly connected to:
● Lamination sequence (especially for blind and buried vias)
● Stackup planning (materials, thickness, copper distribution)
● Standards and acceptance criteria such as IPC workmanship requirements and via protection styles (e.g., IPC-4761)
In short: design tells the factory what you want; via formation determines whether it will be reliable.
3. Overview: The Core Stages of Via Formation
Most vias formed in PCBs follow a universal workflow, even if the details differ by product:
● Drilling (mechanical or laser)
● Hole cleaning & desmear
● Electroless copper deposition (seed layer)
● Electrolytic copper plating (build thickness)
● Optional via enhancement (filling, plugging, capping)
● Etching and final finishing
Think of it as a conversion pipeline:
geometry → cleanliness → conductivity → thickness → protection
If any stage is weak, the via becomes a reliability risk—often invisible until late testing or field use.
4. Via Drilling Methods: How Via Holes Are Created
4.1 Mechanical Drilling (Through-Hole & Larger Blind Vias)
Mechanical drilling uses high-speed CNC spindles and carbide drill bits to create holes through one or more laminated layers. It’s the backbone method for:
● plated through-holes (PTH)
● many standard through vias
● some blind vias (depending on depth and design)
Key concepts:
CNC drilling fundamentals
● The drill follows Excellon/NC drill data.
● Panels are stacked and pinned for throughput and alignment.
● Drill parameters (speed, feed rate, hit count) are carefully managed.
Drill wander and breakout risk
● Bits can “wander” slightly as they enter composite materials (resin + glass weave).
● Poor control can lead to offset holes, reduced annular ring, or partial breakout on inner pads.
Minimum drill size and tolerances
● Smaller holes increase risk: bit wear, debris, and wall roughness become harder to control.
● Tolerance targets tighten as pitch and annular ring shrink.
Aspect ratio constraints (the practical “10:1” rule)
A deeper hole is harder to plate uniformly. Many manufacturers use a practical rule: if the board thickness is too high relative to hole diameter, copper may not build evenly in the center of the via barrel. The more extreme the aspect ratio, the higher the process difficulty and inspection burden.
4.2 Laser Drilling (Microvias & HDI Boards)
Laser drilling exists because mechanical drilling reaches limits in:
● minimum via size
● positional precision for ultra-dense routing
● controlled depth for small blind features
Microvias are typically laser-drilled and are common in HDI designs.
UV vs CO₂ laser drilling
● Different lasers interact differently with copper and resin.
● Selection depends on materials and whether copper is used as a “stop layer.”
Why lasers enable very small vias
Laser drilling can create extremely small, shallow features where a mechanical bit would break or cause damage.
Depth control and layer targeting
Laser microvias are often drilled to a specific layer (blind by nature), which means the lamination sequence and copper target layers must be planned precisely.
Limitations
Laser drilling introduces its own risks:
● heat-affected zones
● resin recession
● the need for exceptionally clean desmear and plating to avoid voids
4.3 Drilling Accuracy and Reliability
Drilling is not only “positioning”—it sets the stage for plating integrity.
● Annular ring: if the hole is off-center, you lose pad ring margin, increasing crack risk.
● Registration: holes must align with inner-layer pads that are buried inside the stack.
● Defects: burrs, debris, smear, and rough walls can all degrade copper adhesion later.
5. Hole Cleaning and Desmear: Preparing Vias for Plating
This is the quiet step that decides whether plating bonds properly.
Where smear and debris come from
During drilling, heat and mechanical action soften resin and smear it across the exposed inner-layer copper. Debris may lodge in the hole and coat surfaces.
Cleaning approaches
● Mechanical cleaning can remove loose debris, but it’s not enough.
● Chemical desmear removes resin smear and conditions surfaces.
● Plasma desmear is often used for HDI and microvias where cleanliness and surface activation are more demanding.
Why poor desmear causes failures
If resin smear or contamination remains:
● electroless copper cannot deposit uniformly
● plating may “skip” or form weak interfaces
● voids and opens appear in vias
● early-life failures show up after thermal stress or vibration
A via can look fine on the outside but fail electrically because the barrel is discontinuous internally.
6. How PCB Vias Are Plated with Copper
This is the core of how vias formed in PCBs become real interconnects.
6.1 Electroless Copper Deposition (Seed Layer)
Why vias cannot be electroplated directly
Electroplating requires current flow. A freshly drilled hole wall is mostly non-conductive resin/glass, so there’s no conductive path to carry plating current.
What electroless copper does
It deposits a very thin, continuous copper layer on the hole wall and exposed internal pads—creating conductivity so electroplating can begin.
Uniformity challenges
Deep vias and complex stacks make it harder to create an even seed layer. Any discontinuity becomes a future weak point.
6.2 Electroplating: Building Via Wall Thickness
Once a conductive seed layer exists, electroplating builds copper thickness on:
● the hole wall (via barrel)
● the panel surface (which later becomes traces/pads after imaging/etching)
Cathodic plating, simplified
The PCB is placed in a plating bath and connected electrically so copper deposits onto its conductive surfaces.
Throwing power (simple engineering definition)
Throwing power describes how well copper plating reaches into the depth of a hole compared to the surface. Poor throwing power leads to:
● thick copper near the hole entrance
● thin copper in the center of the barrel
That thin zone is where fatigue cracks most likely to start.
Barrel copper vs surface copper
These are not the same thing:
● Surface copper affects trace current capacity and etch behavior.
● Barrel copper is the via’s structural backbone. It must be robust enough to survive thermal expansion mismatch across layers.
6.3 Plating Challenges by Via Type
● Through-hole vias: deeper holes, higher aspect ratios, more throwing-power sensitivity.
● Blind vias: controlled depth improves plating reach, but adds lamination complexity.
● Buried vias: formed inside sub-laminations; inspection access is harder.
● Microvias: shallow, small, often require copper filling or careful control to prevent voids and weak interfaces.
7. Via Formation Differences by Via Type
7.1 Through-Hole Via Formation
Classic workflow:
drill → desmear → electroless copper → electroplate → pattern/etch
Advantages:
● fewer lamination steps
● mature process control across industry
● easier inspection and verification
Where they struggle:
● high aspect ratio
● very small diameters in thick boards
● high-speed PCB designs where stubs create SI issues
7.2 Blind Via Formation
Blind vias connect outer layers to one or more inner layers.
Key differences:
● sequential lamination may be needed
● controlled depth drilling (mechanical or laser)
● plating must be consistent at the “stop layer”
Reliability concerns:
● depth control errors
● insufficient desmear at the via bottom
● non-uniform plating at layer interfaces
7.3 Buried Via Formation
Buried vias connect internal layers only and are formed inside sub-laminated cores.
Key differences:
● requires sub-lamination strategy
● demands accurate alignment between lamination stages
● inspection is less direct once buried inside the stack
7.4 Microvia Formation (HDI Flow)
Typical flow:
● lamination stage
● laser drill microvias
● desmear/clean
● plate and often fill depending on design
Microvias are naturally shallow, which helps throwing power. But they require excellent cleanliness and process stability because the features are so small.
Filled vs hollow microvias
● Hollow microvias can work in some designs, but may be limited in stacking or via-in-pad use.
● Filled microvias support stacking and flat pad surfaces, but add process cost and control requirements.
8. Via Filling, Plugging, and Capping: Enhancing Via Performance
8.1 Why vias are filled
Common reasons:
● prevent solder from wicking into vias (especially near pads)
● improve thermal transfer (thermal vias)
● enable via-in-pad for dense BGAs and compact layouts
● improve surface planarity and assembly yield
8.2 Fill materials (practical view)
● Non-conductive epoxy fill: often used to prevent wicking and improve planarity.
● Conductive copper fill: supports performance and stacking in demanding HDI designs, usually higher process complexity.
8.3 Tenting, plugging, capping (when to use what)
● Tented vias: solder mask covers the via; good for preventing solder intrusion in less demanding cases.
● Plugged vias: resin or mask plugs the hole; improves solder control.
● Capped vias: plated or finished to create a closed, flat surface—useful for via-in-pad and assembly yield improvements.
9. Via Formation and Signal Integrity
For high-speed designs, via formation isn’t just reliability—it’s electrical behavior.
Stub effects in through-hole vias
A through via often leaves unused barrel length (a stub) that behaves like an antenna or resonator at high frequencies, contributing to reflections and EMI.
Why unused barrels cause EMI
They introduce impedance discontinuities and can radiate, especially in GHz-class layouts.
Back-drilling, explained simply
Back-drilling removes unused via barrel length after plating to reduce stubs and improve signal integrity.
Microvias vs through vias for GHz designs
Microvias reduce stub length naturally and are often favored in high-speed routing zones, but they require HDI-capable manufacturing and tighter process control.
10. Via Formation and Thermal Performance
Vias can also be thermal pathways.
Copper thickness and heat flow
Thicker, well-plated via barrels conduct heat better and remain mechanically stronger under thermal cycling.
Via arrays under thermal pads
Thermal via arrays are commonly used under power devices to dissipate heat to inner planes or the opposite side.
Filled vs unfilled thermal vias
● Unfilled vias can wick solder and reduce assembly yield if placed in pads without protection.
● Filled vias help planarity and improve heat path consistency but add process complexity.
Manufacturing trade-offs
More and smaller thermal vias can improve heat spreading—but increase drilling/plating workload and cost. The goal is a balanced design that meets thermal needs without creating unnecessary manufacturing burden.
11. Common Via Formation Defects and Failure Modes
This is the section many buyers wish they understood earlier.
Voids in via barrels
Often linked to:
● poor desmear/cleanliness
● plating chemistry control
● trapped gas or insufficient wetting during deposition
Cracked copper plating
Usually a fatigue issue caused by:
● thin barrel copper
● weak adhesion
● high thermal cycling stress from material mismatch
Blow holes and outgassing
Trapped contamination or moisture can expand during thermal exposure, creating defects in plating or surrounding resin.
CAF (Conductive Anodic Filament)
A failure mode where conductive paths form through dielectric under bias and moisture conditions. Via spacing, cleanliness, resin quality, and process control all matter.
How a professional factory controls and guarantee:
● drilling quality and wall condition
● desmear effectiveness
● electroless copper continuity
● electroplating uniformity
● inspection gates (microsection, electrical test, AOI where applicable)
● traceability and process monitoring
12. Design Rules That Directly Affect Via Manufacturability
Via reliability is partly designed, not only manufactured.
Key rules that matter:
● Minimum via size vs board thickness: avoid extreme aspect ratios unless necessary.
● Annular ring margin: keep enough pad ring to tolerate registration variation.
● Aspect ratio limits by via type: microvias are shallow; through vias can become challenging in thick boards.
● Consult manufacturers early: especially for HDI stacking, via-in-pad, high-frequency material stacks, and tight tolerances.
A quick reality check: if the via spec is “possible” but not stable, yield becomes your hidden cost.
13. Cost Impact: How Via Formation Choices Affect PCB Price
Via formation is one of the most cost-sensitive parts of the PCB manufacturing process because it impacts cycle time, equipment selection, and inspection.
Major cost drivers
● Drilling method: laser microvia drilling costs more per feature than mechanical drilling.
● Sequential lamination: each lamination stage adds time, risk, and process steps.
● Filling/capping: adds materials, process control, and surface planarity checks.
When microvias reduce total cost
In some compact designs, HDI can reduce overall layer count or routing complexity. Even if microvias cost more, fewer layers or smaller boards can lower total system cost.
Practical cost-optimization strategies
● avoid excessive via counts where a plane or routing change solves it
● keep via sizes would be well manufactured and consistent across the design
● use HDI features only where they reduce size or performance risk
● confirm which vias must be filled vs which can be tented
14. FAQs: How Are Vias Formed in PCBs?
How are PCB vias plated?
Vias are plated: first, creating a thin electroless copper seed layer, then building thickness through electrolytic copper electroplating.
Are vias drilled or etched?
Most vias are drilled (mechanical or laser). Etching shapes copper patterns on copper layers but doesn’t create typical via holes.
Why do microvias need laser drilling?
The diameter is too tiny and controlled depth are not practical for mechanical bits at scale, and laser offers better feature control for HDI.
What causes via failure?
Common causes include voids, thin barrel copper, poor adhesion, misregistration, resin smear, and thermal fatigue from cycling.
Are filled vias always better?
Not always. Filled vias improve planarity and prevent wicking, but they add cost and process complexity. Use them where assembly density or thermal needs require them.
15. Conclusion: Via Formation Is a Manufacturing Decision, Not Just a Design Choice
Vias are the hidden backbone of a PCB. When vias formed in PCBs are created through a disciplined workflow—drilling accuracy, effective desmear, continuous electroless copper, uniform electroplating, and appropriate filling/protection—you get stable interconnects that survive real-world stress. When those steps are weak, failures can show up late, expensively, and unpredictably.
The best results come when designers and manufacturers collaborate at earlys stage—especially for HDI, via-in-pad, thick boards, high-speed routing, and harsh environments. If you want a manufacturing-ready review of your via strategy, working with an experienced PCB Fabrication Service partner can turn via decisions into predictable yield and reliability.
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About the auther:
Sonic Yang
As a major of Electronics and Mechanical Automation, Sonic has been engaged in PCB design, R&D, manufacturing of eletronics for around 22 years, as engineering director and coordinates with supply chain(components&CNC parts), providing professional supports and consults for global customers.
